Flash memory is a type of electronic memory media which can be rewritten and hold its content without power. Unlike dynamic random access memory (DRAM) and static random access memory (SRAM) memory chips, in which a single byte can be erased, flash memory is typically erased and written in fixed multi-bit blocks or sectors. Evolving out of electrically erasable read only memory (EEPROM) chip technology, which can be erased in place, flash memory is less expensive and more dense. This new category of EEPROMs has emerged as an important non-volatile memory which combines the advantages of EPROM density with EEPROM electrical erasability.
Conventional flash memories are constructed in a cell structure wherein a single bit of information is stored in each cell. In such single bit memory architectures, each cell typically includes a metal oxide semiconductor (MOS) transistor structure having a source, a drain, and a channel in a substrate or P-well, as well as a stacked gate structure overlying the channel. The stacked gate may further include a thin gate dielectric layer (sometimes referred to as a tunnel oxide) formed on the surface of the P-well. The stacked gate also includes a polysilicon floating gate overlying the tunnel oxide and an interpoly dielectric layer overlying the floating gate. The interpoly dielectric layer often is a multilayer insulator such as an oxide-nitride-oxide (ONO) layer having a nitride layer sandwiched between two oxide layers. Lastly, a polysilicon control gate overlies the interpoly dielectric layer.
Flash memory devices require a common source line, for example, to provide a connection to ground voltage (e.g., a VSS contact) during a read operation. Generally, the VSS contact is formed between stacked gate layers of the flash memory device. As is known in the art, contacts are among the most difficult features to pattern in semiconductor manufacturing. Not only are they smaller than any other circuit structure (except gates), but their images are intrinsically 3-dimensional, with the same contact having minimum feature size in both x and y direction and the laws of diffraction reducing the range of focus along the z-direction.
In a conventional method of forming the VSS contact in a flash memory device, a gate oxide layer, a floating gate polysilicon layer, an inter-gate insulating layer and a control gate polysilicon layer are sequentially formed on a semiconductor substrate. Through photolithographic processes, the stacked layers are patterned to form a stacked gate pattern, e.g., a series of stacked gate layers. Impurities are implanted into the substrate using the stacked gate pattern as an implanting mask to form source/drain regions outside of the stacked gate pattern, and an interlayer insulating layer is deposited on the resulting structure. Using a photoetching process, the interlayer insulating layer is patterned between stacked gate layers to form a circular contact hole, exposing a predetermined region of the semiconductor substrate. A conductive layer is then deposited in the contact hole and on the interlayer insulating layer. A planarization process such as an etch-back or a chemical mechanical polish is carried out to leave the conductive layer in the contact hole and remove the portion of the conductive layer that is outside of the contact hole, thereby forming the VSS contact.
Referring to FIG. 1, a stacked gate pattern 10 of a prior art flash memory device is illustrated. A VSS contact 12 is patterned between a first stacked gate layer 14 and a second stacked gate layer 16. As stated previously, the VSS contact 12 typically is circular in shape.
A pervasive trend in modern integrated circuit manufacture is to produce semiconductor devices, such as flash memory devices, that are as small as possible. The reduction in size of flash memory devices requires high resolution technology and a sufficient depth of focus (DOF), particularly in the formation of contact holes. DOF is the range of lens-wafer distances over which line widths are maintained within specifications and resist profiles are adequate. As flash memory devices are reduced in size, each stacked gate layer 14, 16 of the stacked gate pattern 10 is formed closer to adjacent stacked gate layers, thus requiring a smaller VSS contact 12. As the VSS contact 12 is reduced in size, DOF margin becomes an issue in patterning the VSS contact. In present integrated circuit fabrication, DOF is becoming so small that it is a concern as to whether optical wafer steppers are capable of maintaining the image in focus. This problem is evident in forming components having small feature size, such as contact holes.
Another concern in integrated circuit manufacture is the lateral positioning between layers comprising the integrated circuit, which is known as overlay. As feature sizes shrink, the overlay tolerances must become smaller in order to minimize the creation of defective devices. The reduction in size of the flash memory device requires the VSS contact 12 and adjacent stacked gate layers 14, 16 to be in closer proximity to one another, thus creating overlay margin issues.
As a result, there exists a need in the art for a method of patterning a VSS contact in a flash memory device that improves the DOF margin and the overlay margin within the stacked gate layer.